The present invention relates to a semiconductor device fabrication method using Group III-V nitride semiconductors, and more particularly relates to a semiconductor device fabrication method in which an isolating insulator film which isolates semiconductor elements from each other is formed by a selective oxidation technique.
The Group III-V nitride semiconductors, which have material characteristics such as high breakdown electric field strength, high thermal conductivity, and high electron saturation velocity, are promising materials for high-frequency power devices. Examples of the Group III-V nitride semiconductors currently used include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) and indium aluminum gallium nitride (InAlGaN). Particularly, in a semiconductor device in which an AlGaN/GaN heterojunction structure is used, electrons accumulate in the vicinity of the heterojunction interface to form a so-called two-dimensional electron gas layer, thereby achieving a high electron mobility.
A conventional heterojunction field effect transistor (HFET) in which an AlGaN/GaN heterojunction is used includes an undoped GaN layer and an AlGaN layer formed on the GaN layer and doped with a donor impurity. Formed on the AlGaN layer are a gate electrode, a source electrode and a drain electrode. By adopting the AlGaN/GaN heterojunction, the conventional HFET achieves an electron velocity more than two times higher than that of a HFET which uses a heterojunction of aluminum gallium arsenide (AlGaAs) and indium gallium arsenide (InGaAs), in a high electric field of about 1×105 V/cm. In addition, a two-dimensional electron gas layer, formed in the GaN layer near the interface with the AlGaN layer, is spaced apart from the donor impurity in the AlGaN layer, which enables a decrease in source resistance components as well as allowing the high electron mobility. Furthermore, in the field effect transistor structured in this manner, the distance between the gate electrode and the two-dimensional electron gas layer may be designed to be about several tens nm, such that the short channel effect is suppressed even when the gate length is shortened, thereby resulting in good saturation characteristics while achieving a downsizing of the HFET.
In fabricating the conventional HEFT with this structure, a method which is called a selective oxidation method may be used to form an isolating insulator film which isolates transistor elements from each other. In the selective oxidation method, an oxidation protection film is selectively formed on the device structure of the stacked Group III-V nitride semiconductors so that the oxidation protection film covers the active region, and thereafter a heat treatment is performed in an oxidizing atmosphere to oxidize part of the device structure which is exposed through the oxidation protection film. In this manner, an isolating insulator film is formed out of the oxides of the Group III-V nitride semiconductors. After removing the oxidation protection film, the gate electrode, the drain electrode and the source electrode are formed in the active region of the device structure, thereby obtaining the finished conventional HFET.
In the conventional HFET fabrication method, a technique in which silicon is used as material for the oxidation protection film has been known.
In the conventional HFET fabrication method, also known is a technique in which, with silicon used as material for the oxidation protection film, a heat treatment is performed in an oxidizing atmosphere whose temperature is 900° C. or higher, thereby diffusing the silicon from the oxidation protection film into the GaN layer. Use of this technique allows the impurity concentration of the GaN layer to increase, which reduces the contact resistance of the source and drain electrodes.
However, in the known HFET fabrication method, if the selective oxidation process is performed in the oxygen atmosphere at a temperature of about 900° C., the oxidation treatment needs to be carried out for more than 4 hours in order to form an isolating insulator film having a sufficient thickness for device isolation. Moreover, the oxidation treatment may have to be performed for more than 12 hours depending on the components of the semiconductor multilayer structure. Specifically, in the process step of forming the isolating insulator film, if the contact resistance is decreased by diffusing the silicon, the work efficiency of the isolating-insulator-film formation process step decreases, which leads to an increase in the HFET product cost.
Further, if the temperature of the oxygen atmosphere is increased in order to reduce the oxidation treatment time, the amount of silicon which diffuses from the oxidation protection film increases, such that the silicon diffusion extends from the surface of the device structure into the inside thereof, thereby converting the structure into an n-type semiconductor layer. As a consequence, the electric characteristics of the device structure of the Group III-V nitride semiconductors are destroyed. This destruction produces problems such as an increase in the gate current leakage and a decrease in the electron mobility of the two-dimensional electron gas layer.